Multiple reads from the same register are also possible with the TMP114. Figure 7-15 shows how the controller

can repeatedly read from the same register when the Auto-Increment bit in the control register is set to 0b. When

reading from the same register in the same transaction the device must be read from faster than the timeout

period.

S

A6

A5

A4

A3

A2

A1

A0

0

A

START

Target Address

0

0

0

P3

P2

P1

P0

A

0

R/W

ACK from Target

Register Pointer (N)

ACK from Target

D14 D13 D12 D11 D10 D9

D8

A

D15

D6

D5

D4

D3

D2

D1

D0

A

D7

ACK from Controller

ACK from Controller

Data from Register N MSB

Data from Register N LSB

RS A6

A5

A4

A3

A2

A1

A0

1

A

Re-START

Target Address

R/W

ACK from Target

Target controls SDA line

Controller controls SDA line

Auto-Increment

Must be 0h

D14 D13 D12 D11 D10 D9

D8

A

D15

D6

D5

D4

D3

D2

D1

D0 NA

D7

P

STOP

ACK from Controller

NACK from Controller

Data from Register N MSB

Data from Register N LSB

Figure 7-15. Repeated Read from Single Register

the TMP114 also supports a continuous read from sequential registers. By setting the Auto-Increment bit in the

control register to 1b, the TMP114 will increment the address pointer after each word of data is read from the

device. This allows the controller to read multiple register values in the same transaction as shown in Figure

7-16. Currently, using a burst read will not clear the Alert Status register. It is recommended to use single register

reads to clear Alert Status register contents.

S

A6

A5

A4

A3

A2

A1

A0

0

A

START

Target Address

0

0

0

P3

P2

P1

P0

A

1

R/W

ACK from Target

Register Pointer (N)

ACK from Target

D14 D13 D12 D11 D10 D9

D8

A

D15

D6

D5

D4

D3

D2

D1

D0

A

D7

ACK from Controller

ACK from Controller

Data from Register N MSB

Data from Register N LSB

RS A6

A5

A4

A3

A2

A1

A0

1

A

Re-START

Target Address

R/W

ACK from Target

Target controls SDA line

Controller controls SDA line

Auto-Increment

Must be 0h

D14 D13 D12 D11 D10 D9

D8

A

D15

D6

D5

D4

D3

D2

D1

D0 NA

D7

P

STOP

ACK from Controller

NACK from Controller

Data from Register N+1 MSB

Data from Register N+1 LSB

Figure 7-16. Burst Read from Multiple Registers

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TMP114

SNIS214 – JUNE 2021

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