TMP114 datasheet(20/43 Pages) TI

20 / 43 page

Target controls SDA line

Controller controls SDA line

I2C Bus

Target

Address

Control

MSB Data

to Register

LSB Data

to Register

CRC

MSB Data

to Register

LSB Data

to Register

CRC

First CRC determined by Target Address, Pointer Register, MSB, and LSB data bytes

Subsequent CRC bytes determined by

preceding MSB and LSB bytes.

Figure 7-13. CRC Enabled Write

7.5.4.3 Reads

For a read operation the controller sends a START condition, followed by the target address with the R/W bit

set to 0b (signifying a write). The target acknowledges the write request, and the controller sends the command

byte with the Auto-Increment bit and Register Pointer. After the Control Register, the controller will initiate a

restart followed by the target address with the R/W bit set to 1b (signifying a read). The controller will continue

to send out clock pulses but releases the SDA line so that the target can transmit data. At the end of every byte

of data, the controller sends an ACK to the target, letting the target know that it is ready for more data. Once

the controller has received the number of bytes it is expecting, it sends a NACK, signaling to the target to halt

communications and release the SDA line. The controller follows this up with a STOP condition. Reading from a

non-indexed register location will return 00h.

Figure 7-14 shows an example of reading a single word from a target register.

START

Target Address

R/W

ACK from Target

D14 D13 D12 D11 D10 D9

D15

D0 NA

STOP

ACK from Controller

NACK from Controller

Data from Register N MSB

Data from Register N LSB

RS A6

Re-START

Target Address

R/W

ACK from Target

Target controls SDA line

Controller controls SDA line

Auto-Increment

Must be 0h

Figure 7-14. Read from Single Register

TMP114

SNIS214 – JUNE 2021

www.ti.com

Submit Document Feedback

Product Folder Links: TMP114

TMP114 Datasheet(PDF) 20 Page - Texas Instruments

TMP114 Datasheet(HTML) 20 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL