CLH

CLL

IN

OUT

Clamp

diode

JFET

+6 V

±6 V

+

±

D1

D2

Q1

Q2

Input clamp

circuit

Output

clamp circuit

VS+

VS-

Output

pre-driver

+

clamp

Figure 8-3. External Input Clamp Circuit

• Output Clamp Circuit:

– The output protection circuit prevents the stages following the BUF802 from being overdriven and also

ensures that the BUF802 recovers rapidly from a saturated state resulting from an input or output

overdrive condition. In a typical data-acquisition system, the BUF802 would be followed by a variable

gain amplifier (VGA). High-speed VGAs are typically designed on 5 V processes making it susceptible to

potential damage from the 12 V BUF802.

– The voltage applied to the CLH and CLL pins dictate the maximum output swing of the BUF802. As shown

When the clamps are disabled, the maximum output swing is limited by the output swing specification

described in Section 6.5. The response time and accuracy of the output clamp is shown in Section 6.7.

value. To prevent signal degradation, maintain at least a 1.5 V difference between the expected peak

output voltage and the clamp voltage applied at the CLH and CLL pins. Figure 8-4 shows the relation

Clamp Voltage (V)

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

-80

-75

-70

-65

-60

-55

-50

-45

-40

THD for 500 MHz

THD for 1 GHz

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BUF802

SBOS998 – JUNE 2021

Copyright © 2021 Texas Instruments Incorporated

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