9.2.2 Sub-500 MHz Oscilloscope Front-End

200 kŸ

CF

R

R

R

between DC and AC

Ÿ

Offset

control

DAC

BUF802

BUF802

+6 V

+

±

Precision

Amp

R

R

R

R

R

R

R

R

OPA4872

+

-

Logic

A0 A1

R

R

R

R

To FDA

800 kŸ

1 MŸ

C nF

±

V

80 k

80 k

IN

Figure 9-5. Sub-500 MHz Oscilloscope Front-End

9.2.2.1 Design Requirements

The design requirements and the previous image are required for multiple applications at a minimum.

9.2.2.2 Detailed Design Procedure

Do not repeat the full step-by-step design for multiple applications, only describe the key differences between the

applications.

9.2.3 500 MHz Oscilloscope Front-End

2.5 V

+OUT

±

OUT

OUT Aux OUT Aux

LMH6518

Trigger

Circuit

5 V

Circuit

ADC A

Clocking Subsystem

16 LVDS

16 LVDS

FPGA or

ASIC

SYNC~

SPI

ADC08D1520

ADC B

800 kŸ

330 pF / 400 V

56 pF

R

Offset Control

DAC

+8 V

±

V

+

-

+

-

Precision

Amp

+8 V

±

V

CLH

CLL

IN

OUT

R_Bias

In_Bias

In_Aux Aux_

Bias

10 m

2.5 V

2.5 V

F

F

200 kŸ

2 k

2 k

1 k

1 k

1 kŸ

1 kŸ

+IN

±

IN

Input

Figure 9-6. 500 MHz Oscilloscope Front-End

9.2.3.1 Design Requirements

The design requirements and the previous image are required for multiple applications at a minimum.

9.2.3.2 Detailed Design Procedure

Do not repeat the full step-by-step design for multiple applications, only describe the key differences between the

applications.

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BUF802

SBOS998 – JUNE 2021

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