ACE25AA320GFMTH datasheet(23/67 Pages) ACE

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ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

Quad Output Fast Read (6BH )

The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each

bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per

clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in Figure 9. The first byte

addressed can be at any location. The address is automatically incremented to the next address after

each byte of data is shifted out.

Dual I/O Fast Read(BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the

capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI

and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted

out 2-bit per clock cycle from SI and SO. The command sequence is shown in Figure 10. The first byte

addressed can be at any location. The address is automatically incremented to the next address after

each byte of data is shifted out.

Dual I/O Fast Read with “Continuous Read Mode”

The Dual I/O Fast Read command can further reduce command overhead through setting the

“Continuous Read Mode” bits (M7- 0) after the input 3-byte address (A23-A0). If the “Continuous Read

Mode” bits (M5- 4) =(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then

lowered) does not require the BBH command code. The command sequence is shown in figure 10a. If the

“Continuous Read Mode” bits (M5- 4) do not equal (1, 0), the next command requires the first BBH

command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be

used to reset (M5- 4) before issuing normal command.

Figure9. Quad Output Fast Read Sequence Diagram

ACE25AA320GFMTH Datasheet(PDF) 23 Page - ACE Technology Co., LTD.