ACE25AA320GFMTH datasheet(27/67 Pages) ACE

27 / 67 page

ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

Quad I/O Word Fast Read(E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the

lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in

followed Figure 12. The first byte addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of

Status Register (S9) must be set to enable for the Quad I/O Word Fast read command.

Quad I/O Word Fast Read with “Continuous Read Mode”

The Quad I/O Word Fast Read command can further reduce command overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read

Mode” bits (M5- 4) =(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and

then lowered) does not require the E7H command code. The command sequence is shown in followed

Figure 12a. If the “Continuous Read Mode” bits (M5- 4) do not equal (1, 0), the next command requires

the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset

command can be used to reset (M7-0) before issuing normal command.

Figure12.Quad I/O Word Fast Read Sequence Diagram (M5-

4≠(1, 0))

Figure12a.Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))

ACE25AA320GFMTH Datasheet(PDF) 27 Page - ACE Technology Co., LTD.