ACE25AA320GFMTH datasheet(31/67 Pages) ACE

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ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

The command sequence is shown in Figure 15. If more than 256 bytes are sent to the device, previously

latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within

the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the

requested ad- dresses without having any effects on the other bytes of the same page. CS# must be

driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page

Program command is not executed.

As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is

initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check

the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed

Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset.

A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3,

BP2, BP1, BP0) will not be executed.

Sector Erase (SE) (20H)

The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase

(SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI.

Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven

low for the entire duration of the sequence.

Figure15. Quad Page Program Sequence Diagram

ACE25AA320GFMTH Datasheet(PDF) 31 Page - ACE Technology Co., LTD.