ACE25AA320GFMTH datasheet(5/67 Pages) ACE

5 / 67 page

ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

Device Operation

The ACE25AA320G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip

Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are

supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of

SCLK.

Dual SPI

The ACE25AA320G supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O

Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the

device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins

become bidirectional I/O pins: IO0 and IO1.

Quad SPI

The ACE25AA320G supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O

Fast Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be

transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI

command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins

become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status

QPI

The ACE25AA320G supports Quad Peripheral Interface (QPI) operations only when the device is

switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command.

The QPI mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and

QPI mode are exclusive. Only one mode can be active at any given times. “Enable the QPI (38H)” and

“Disable the QPI (FFH)” commands are used to switch between these two modes. Upon power-up and

after software reset using “”Reset (99H)” command, the default state of the device is Standard/Dual/Quad

SPI mode. The QPI mode requires the non- volatile Quad Enable bit (QE) in Status Register to be set.

Hold

The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the

operation of write status register, programming, or erasing in progress .

The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK

signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD

condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD

operation will not end until SCLK being low).

ACE25AA320GFMTH Datasheet(PDF) 5 Page - ACE Technology Co., LTD.