ACE25AA320GFMTH datasheet(33/67 Pages) ACE

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ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

The 32KB Block Erase command sequence: CS# goes low→sending 32KB Block Erase command→

3-byte address on SI→CS# goes high. The command sequence is shown in Figure17. CS# must be

driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block

Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle

(whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be

read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the

self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a

block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1 & 1.1) will not

be executed.

64KB Block Erase (BE) (D8H)

The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable

(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The

64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and

three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE)

command. CS# must be driven low for the entire duration of the sequence.

Figure17. 32KB Block Erase Sequence Diagram

Figure17a. 32KB Block Erase Sequence Diagram (QPI)

ACE25AA320GFMTH Datasheet(PDF) 33 Page - ACE Technology Co., LTD.