ACE25AA320GFMTH datasheet(10/67 Pages) ACE

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ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

SRP1

SRP0

WP#

Status Register

Description

Software Protected

The Status Register can be written to after a Write

Enable command, WEL=1.(Default)

Hardware Protected

WP#=0, the Status Register locked and cannot be

written to.

Hardware Unprotected

WP#=1, the Status Register is unlocked and can be

written to after a Write Enable command, WEL=1.

Power Supply Lock-

Down(1)(2)

Status Register is protected and cannot be written to

again until the next Power-Down, Power-Up cycle.

One-Time Program(2)

Status Register is permanently protected and cannot

be written to.

Notes:

When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.

This feature is available on special order.

QE bit.

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad

operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE bit

is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard

SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground).

LB bit.

The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write

protect control and status to the Security Registers. The default state of LB is 0, the security registers are

unlocked. LB can be set to 1 using the Write Register instruction. LB is One Time Programmable, once it’s

set to 1, the Security Registers will become read-only permanently.

CMP bit.

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the

BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory

Protec tion table for details. The default setting is CMP=0.

SUS bit.

The SUS bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program

Suspend (75H or B0H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH or 30H)

command or during power-down & power-up cycle.

ACE25AA320GFMTH Datasheet(PDF) 10 Page - ACE Technology Co., LTD.

ACE25AA320GFMTH Datasheet(HTML) 10 Page - ACE Technology Co., LTD.

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