| Electronic Components Datasheet Search |
|
MPC755 Datasheet(PDF) 18 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
MPC755 Datasheet(HTML) 18 Page - NXP Semiconductors |
|
18 / 56 page ![]() MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 18 Freescale Semiconductor Electrical and Thermal Characteristics Table 11. L2CLK Output AC Timing Specification At recommended operating conditions (see Table 3) Parameter Symbol All Speed Grades Unit Notes Min Max L2CLK frequency fL2CLK 80 450 MHz 1, 4 L2CLK cycle time tL2CLK 2.5 12.5 ns L2CLK duty cycle tCHCL/tL2CLK 45 55 % 2, 7 Internal DLL-relock time 640 — L2CLK 3, 7 DLL capture window 0 10 ns 5, 7 L2CLK_OUT output-to-output skew tL2CSKW —50 ps 6, 7 L2CLK_OUT output jitter — ±150 ps 6, 7 Notes: 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUT, and L2SYNC_OUT pins. The L2CLK frequency-to-core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. The maximum L2LCK frequency will be system dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading. 2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage. 3. The DLL-relock time is specified in terms of L2CLK periods. The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in ns. Relock timing is guaranteed by design and characterization. 4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL. 5. Allowable skew between L2SYNC_OUT and L2SYNC_IN. 6. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLK_OUT and the L2 address/data/control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis. 7. Guaranteed by design. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |