MPC755 datasheet(22/56 Pages) NXP

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

Electrical and Thermal Characteristics

4.2.5

IEEE 1149.1 AC Timing Specifications

Table 13 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 12 through

Figure 15.

Figure 11 provides the AC test load for TDO and the boundary-scan outputs of the MPC755.

Figure 11. AC Test Load for the JTAG Interface

Table 13. JTAG AC Timing Specifications (Independent of SYSCLK) 1

At recommended operating conditions (see Table 3)

Parameter

Symbol

Min

Max

Unit

Notes

TCK frequency of operation

fTCLK

016

MHz

TCK cycle time

tTCLK

62.5

—

TCK clock pulse width measured at 1.4 V

tJHJL

—

TCK rise and fall times

tJR, tJF

TRST assert time

tTRST

—

Input setup times:

Boundary-scan data

TMS, TDI

tDVJH

tIVJH

—

Input hold times:

Boundary-scan data

TMS, TDI

tDXJH

tIXJH

—

Valid times:

Boundary-scan data

TDO

tJLDV

tJLOV

—

Output hold times:

Boundary-scan data

TDO

tJLDH

tJLOH

—

TCK to output high impedance:

Boundary-scan data

TDO

tJLDZ

tJLOZ

4, 5

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load (see Figure 11).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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