MPC755 datasheet(20/56 Pages) NXP

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 8 shows the L2 bus input timing diagrams for the MPC755.

Figure 8. L2 Bus Input Timing Diagrams

L2SYNC_IN to high impedance:

All outputs when L2CR[14–15] = 00

All outputs when L2CR[14–15] = 01

All outputs when L2CR[14–15] = 10

All outputs when L2CR[14–15] = 11

tL2CHOZ

—

2.4

2.6

2.8

3.0

3, 5

Notes:

1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD.

2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of

the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.

3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the

signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load (see

Figure 10).

4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous BurstRAMs,

L2CR[14–15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14–15] = 11 is

recommended.

5. Guaranteed by design and characterization.

6. Revisions prior to Rev. 2.8 (Rev. E) were limited in performance and did not conform to this specification. For more

information, refer to Section 10.2, “Part Numbers Not Fully Addressed by This Document.”

Table 12. L2 Bus Interface AC Timing Specifications (continued)

At recommended operating conditions (see Table 3)

Parameter

Symbol

All Speed Grades

Unit

Notes

Min

Max

L2SYNC_IN

L2 Data and Data

VM = Midpoint Voltage (L2OVDD/2)

tDVL2CH

tDXL2CH

tL2CR

tL2CF

Parity Inputs

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