TMP126 datasheet(18/45 Pages) TI

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8.5.2.1 Command Word Structure

Figure 8-10 shows that the command word can be divided into 6 discrete sections detailed below.

R/W

Peripheral controls SIO line

Controller controls SIO line

Auto Increment

X CRC L4

R/W

Sub-Address

CRC Data Block Length

CS Pulled low

CRC Enable

Don’t Care

Figure 8-10. TMP126 Command Word

8.5.2.1.1 Don't Care

Bit15 of the command word is a don't care and the TMP126 will ignore this bit.

8.5.2.1.2 CRC Enable

Bit14 of the command word is the CRC enable bit. Setting this bit to 1b will enable the CRC checksum at the end

of the communication as described in the CRC section.

8.5.2.1.3 CRC Data Block Length

Bits[13:10] of the command word is the CRC data block length. These bits are used to indicate how long the

transaction will be when the CRC checksum is used. If this field is set to 0h or a value larger than Ah, the CRC

enable will be ignored.

8.5.2.1.4 Auto Increment

Bit9 of the command word is the auto-increment bit.

Setting this bit to '1' will cause the address pointer of the TMP126 to increment by after every word of data on

a read or write transaction. If the bit is set to '0', the address pointer is not incremented and reads/writes will

continue to only apply the Sub-Address specified in the command word.

8.5.2.1.5 Read/Write

Bit8 of the command word is the read/write bit.

Setting this bit to '1' will issue a read command. During a read command the TMP126 will control the SI/O pin

after the command word. Setting this bit to '0' will issue a write command. During a write command the controller

will control the SI/O pin and the TMP126 will tri-state the SI/O pin.

8.5.2.1.6 Sub-Address

Bits[7:0] of the command word make up the register Sub-Address.

This is the register map address that will be used for reading or writing data depending on the read/write

bit. Writes to Sub-Addresses outside the register map will be ignored. Reads from Sub-Addresses outside the

TMP126

SNIS209 – JULY 2021

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