TMP126 datasheet(21/45 Pages) TI

21 / 45 page

R/W

Peripheral controls SIO line

Controller controls SIO line

Auto Increment

Sub-Address

CS pulled low

D15 D14 D13 D12 D11 D10 D9

Data Word

Data from Register N

D15 D14 D13 D12 D11 D10 D9

Data Word

Data from Register N+1

D15 D14 D13 D12 D11 D10 D9

Data Word

Data from Register N+2

CRC Data Block Length

CRC Enable

Don’t Care

CRC L4

Figure 8-14. Burst Data Read from Multiple Registers

8.5.2.5 Cyclic Redundancy Check (CRC)

The TMP126 has an optional CRC feature to determine the integrity of the data that has been transmitted across

the SPI communication interface. The CRC for the TMP126 is enabled by setting the CRC bit in the command

word to 1b. When enabled, the TMP126 will append a 16 bit CRC checksum to the end the data block for

read transactions. The controller can then compare this checksum to their own calculation and determine if the

transaction was valid. During a write transaction, the host will append the 16-bit CRC checksum. The TMP126

will compare this to its own checksum. If there is a mismatch, the TMP126 will discard the write transaction and

set a CRC fault ALERT to indicate to the host that the transaction failed. The host will need to send the register

settings again to correctly program the TMP126. Reading the Alert_Status register will clear the CRC_Fault bit

and de-assert the ALERT pin.

An overview of a CRC enabled write transaction is shown below with a data block length of 2.

Peripheral controls SIO line

Controller controls SIO line

SIO

Command

Write Data

CRC

CRC determined by Command word and Data Block

Figure 8-15. CRC Enabled Write

An overview of a CRC enabled read transaction is shown below with a data block length of 2.

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TMP126

SNIS209 – JULY 2021

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