AT25SL321 datasheet(51/82 Pages) DIALOG

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AT25SL321

DS-25SL321–112H–2020-10

8.31 Word Read Quad I/O (E7h)

The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP)

directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word

Read Quad I/O instruction. The lowest Address bit (A0) must equal 0 and only two dummy clocks are required

prior to the data output.

Continuous Read Mode

The Word Read Quad I/O instruction can further reduce instruction overhead through setting the Continuous Read

Mode bits (M7-0) after the input Address bits (A23-0), as shown in Figure 8-50. The upper nibble of the (M7-4)

controls the length of the next Word Read Quad I/O instruction through the inclusion or exclusion of the first

byte instruction code. The lower nibble bits of the (M[3:0]) are don’t care (‘X’). However, the IO pins are going to

be high-impedance prior to the falling edge of the first data out clock.

If the Continuous Read Mode bits M[7-4] = Ah, then the next Fast Read Quad I/O instruction (after CS is raised

and then lowered) does not require the E7h instruction code, as shown in Figure 8-51. This reduces the instruction

sequence by eight clocks and allows the Read address to be immediately entered after CS is asserted low. If the

Continuous Read Mode bits M[7:4] do not equal to Ah (1,0,1,0) the next instruction (after CS is raised and then

lowered) requires the first byte instruction code, thus returning to normal operation.

Figure 8-50. Word Read Quad I/O Instruction (Initial instruction or previous set M7-0 ≠ Axh, SPI Mode)

Figure 8-51. Word Read Quad I/O instruction (Previous Instruction set M7-0= Axh, SPI Mode)

SCK

Instruction (E7h)

123

Mode 3

Mode 0

A23-16

A15-8

A7-0

M7-0

Dummy

Byte 1

Byte 2

Byte 3

s switch from

Input to Output

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