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ICS1893AGILF Datasheet(PDF) 94 Page - Integrated Circuit Systems |
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ICS1893AGILF Datasheet(HTML) 94 Page - Integrated Circuit Systems |
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94 / 135 page  ICS1893AG, Rev A 04/14/05 April, 2005 94 Chapter 8 Management Register Set ICS1893AG Data Sheet - Preliminary Copyright © 2005, Integrated Circuit Systems, Inc. All rights reserved. 8.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893AG from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted- Pair Receiver inputs. • One, the ICS1893AG 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state regardless of the Twisted-Pair Receiver input conditions. 8.13.9 Squelch Inhibit (bit 18.0) The Squelch Inhibit bit allows an STA to control the ICS1893AG Squelch Detection in 10Base-T mode. When an STA sets this bit to logic: • Zero, before the ICS1893AG can establish a valid link, the ICS1893AG must receive valid 10Base-T data. • One, before the ICS1893AG can establish a valid link, the ICS1893AG must receive both valid 10Base-T data followed by an IDL. |
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