DA14683 datasheet(39/469 Pages) DIALOG

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Datasheet

Revision 3.4

24-Nov-2020

CFR0011-120-01

39 of 469

DA14683

Bluetooth Low Energy 5.0 SoC with Enhanced Security

FINAL

the DCDC converter comprises 4 outputs:

• Vext which connects to the VDD1V8P pin and deliv-

ers 75 mA when DA14683 is in active and 10 mA

when in Sleep mode. The voltage range of this

power rail is 1.8 V +/- 5%. External devices, such as

Power Amplifiers (PA), Front End Modules (FEMs),

FLASH or sensors can be powered by this rail.

• Vflash which is used for supplying external devices.

This rail’s characteristics are identical to the Vext

one.

• Vradio which powers the RF circuits via a number of

dedicated LDOs. This rail delivers up to 20 mA at 1.4

V and should not be used for supplying external

devices.

• Vcore which supplies the digital core of the

DA14683 and delivers up to 50 mA at 1. 2 V when in

Active mode. This rail should not be used for supply-

ing external devices.

The converter has an asynchronous architecture, i.e.

the on-time of the switches is not determined by an

external clock. Instead, the on-time is determined by a

(dynamically varying) current limit in the external induc-

tor. If one of the output voltages is too low (determined

using clocked comparators) a charge cycle is triggered.

However, it is possible for more than one outputs to be

below minimum at the same time, in which case the

system has to decide which output to charge first. This

is done using a priority select register, which holds the

sequence in which the outputs will be charged. Each

time one or more outputs require a charge cycle, the

system sorts the outputs based on this priority register

and loads this sequence in a four tab shift register.

In order to minimize the ripple voltage on the outputs,

the current limit is dynamically set during operation in

Active mode. This is done by measuring how long each

output is above its minimum value after a charge cycle.

When this time is very long, more charge than required

(given the load current) was stored on the output

capacitor, so the current limit is reduced by one bit

(LSB). However, when the output voltage drops too

quickly, not enough charge was delivered to the output

capacitor, so the current limit is increased by one bit

(LSB).

Figure 13: SIMO DCDC Converter block diagram

DIGITAL

FSM

Charge Initiate

State

Output Select

VBAT

P_SW

IMAX

LEXT

470 nH

N_SW

IL=0

IL=IMAX

FW_SW

CEXT_V18P

= 10 µF

CEXT_V12 =

4.7 µF

CEXT_V18

= 10 µF

CEXT_V14

= 10 µF

OFF CHIP

Set V14

Set VDD1V8

Set VDD1V2

Set VDD1V8P

Vradio

Vflash

Vcore

Vext

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