DA14683 datasheet(68/469 Pages) DIALOG

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Datasheet

Revision 3.4

24-Nov-2020

CFR0011-120-01

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DA14683

Bluetooth Low Energy 5.0 SoC with Enhanced Security

FINAL

8.2 RUNTIME RECONFIGURATION

Associativity and cache line size of cache can be

reconfigured

all

time

writing

the

CACHE_ASSOCCFG_REG

CACHE_LNSIZECFG_REG registers. Reconfiguration

is done without wait state and without flushing the

cache. All the data available in the cache memory are

kept except when the associativity is reduced (4-way ->

2-way and 2-way -> 1-way). In that case typically half

of the data are unaccessible.

8.2.1 Cache Line reconfiguration

The dynamic configuration of the cache line size uses

a physical line size of 8 bytes. When the cache line

size is defined as 16 bytes or 32 bytes, 2 or 4 physical

lines are involved.

Reconfiguration of the cache line occurs only when

lines are replaced. Even if the cache line configuration

is set to 32 bytes, cache lines of 16 bytes may remain

in the cache memory as explained at the example in

Table 22.

8.2.2 TAG memory word

The administration memory word decoding is pre-

sented in Table 23:

8.2.3 Associativity reconfiguration

To enable associativity reconfiguration, the cache

memory is organized into four banks.

Depending on the associativity, the four banks can

operate as 4-way, or be concatenated resulting in

either a 2-way or 1-way cache.

8.3 2 AND 4 WAY REPLACEMENT STRATEGY

The cache controller fills each line of the cache first

starting from way0 to way3. When a line is completely

full, a new way_x victim is chosen in a pseudo random

way.

When a replacement is required, the cache controller

reads the value generated by a pseudo-random num-

ber generated to select which way to replace.

The pseudo-random number generator is realized

using a Linear Feedback Shift Register (LFSR).

8.4 CACHE RESETS

The cache controller has two reset signals connected:

• The HW_RESET. When this reset is activated, all

cache logic and registers are reset to their default

values, while all data in the TAG memories are

cleared and all CACHE_*_REG are set to their reset

values. It takes around 450 AHB cycles to clear the

cache TAG memory.

Table 22: Cache line size reconfiguration example

Step1:

Cache line size = 16 bytes

a. CPU Reads @0x00: Miss

Cache Reads 16 bytes in

Block 0 @0x00

b. CPU Reads @5010: Miss

Cache Reads 16 bytes in

Block 5 @0x10

Step 2:

Cache line size = 32 bytes

a. CPU Reads @0x00: Hit

b. CPU Reads @5010: Hit

c. CPU Reads @5020: Miss

Cache reads 32 bytes in

Block 5 @0x20

Although the configuration

is 32 bytes, the lines of 16

bytes remain in the cache.

Only new lines are 32 bytes.

Step 3:

Cache line size = 32 bytes

a. CPU Reads @0x6000: Miss

Cache reads 32 bytes in

Block 6 @0x00

16-byte cache lines already in

the cache are replaced by the

32-byte cache line.

Table 23: TAG memory layout

Bit 23

Bits 22:2

Bits 1:0

0AHB

address

00: invalid cache line

01: 8 valid bytes

10: 16 valid bytes

11: 32 valid bytes

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