DA14683 datasheet(32/469 Pages) DIALOG

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Datasheet

Revision 3.4

24-Nov-2020

CFR0011-120-01

32 of 469

DA14683

Bluetooth Low Energy 5.0 SoC with Enhanced Security

FINAL

* OPT: optionally on or off, configurable by SW.

** The wake up GPIO must be configured at WKUP_SELECT_Px_REG before going to sleep.

3.6 SECURITY

This section describes the security features supported by the DA14683.

3.6.1 Secure Keys Manipulation

Keys storage and keys manipulation are two very important security features considered that the complete security perimeter of the system is based on trusted keys.

The DA14683 provides the means for the storage and revocation of both public keys used by the Elliptic Curve Controller during authentication/data integrity checks as

well as symmetric keys used by the AES controller during encryption/decryption of data.

3.6.1.1 Asymmetric Keys Area (AKA)

This is memory space in the OTP which contains public keys to be used in secure boot (see section 3.6.2). Since it is public keys to be stored in this area, it is not write

or read protected. Security here is achieved by having a non-modifiable volatile area where keys can be stored.

This memory space can be variable. It is the actual application software as well as the secure secondary bootloader in the OTP that need to know the actual start and

stop addresses of this space. The recommended address space however is 0x7F8E6C0 - 0x7F8E7BF. This space can store up to 8 different 256-bit keys. These keys

are stored into the OTP AKA space during the final product line testing.

To ensure and guarantee that programmed keys are not modified, a separate section in the OTP contains the bit-inverse values of all public keys. For each public key

programmed in the AKA, its inverse also exists. The secure secondary bootloader is responsible for validating the correctness of the public key by XORing the two val-

ues at system boot before allowing for further booting the system in a secure mode. In this way, any modification of the OTP AKA area (i.e. re-programming an existing

key with another value turning 0s into 1s) will not be approved by the XOR operation. The overview of the layout of the OTP is presented in

Figure 9.

Hiberna-

tion

AON_PD=ON

SYS_PD=OFF

BLE_PD=OFF

RAD_PD=OFF

PER_PD=OFF

LDO_USB=OFF

LDO_RET= OFF

LDO_VBAT=OFF

LDO_IO=OFF

BandGap=OFF

LDO_CORE=OFF

SIMO=OFF

LDO_RAD= OFF

LDO_VBAT_RET=OFF

LDO_VBUS_RET=OFF

LDO_IO_RETx=OFF

LDO_SLEEP=OFF

No clocks available.

Before switching into

Deep Sleep mode,

RC32 has to be

selected as low

power clock.

None

Asynchronously to the

BLE using any GPIO. The

toggling activity on any of

the selected pins enables

RC32.

The Hibernation mode assumes a long period of

inactivity for the system and turns off everything

including the clocks.

There is no RAM retained in the system. To actually

power off all RAM cells, if the system is in cached

mode, it must be switched to mirrored mode so that

Cache RAM can be turned off.

Table 9: Power modes and configurations

Power

mode

Power domains

Analog blocks

Clocks available

Retained memory

Wake-up mechanism

Description

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