DA14683 datasheet(66/469 Pages) DIALOG

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Datasheet

Revision 3.4

24-Nov-2020

CFR0011-120-01

66 of 469

DA14683

Bluetooth Low Energy 5.0 SoC with Enhanced Security

FINAL

Interrupt priorities are programmable by the Arm Cor-

tex-M0. The lower the priority number, the higher the

priority level. The priority level is stored in a byte-wide

same priority level follow a fixed priority order using the

interrupt number listed in Table 21 (lower interrupt

number has higher priority level).

To access the Cortex-M0 NVIC registers, CMSIS func-

tions can be used. The input parameter IRQn of the

CMSIS NVIC access functions is the IRQ number. This

can be the IRQ number or (more convenient) the corre-

sponding IRQ name listed in Table 21. The corre-

sponding interrupt handler name in the vector table for

IRQ#15 is e.g. UART_Handler. For more information

on the Arm Cortex-M0 interrupts and the correspond-

ing CMSIS functions, see section 4.2 Nested Vectored

Interrupt Controller on page 4-3 in the Cortex-M0 User

Guide Reference Material.

The Watchdog interrupt is connected to the NMI input

of the processor.

dma_irq

DMA interrupt.

rf_diag_irq

Baseband or Radio diagnostics Interrupt.

trng_irq

True random number generator interrupt.

dcdc_irq

DCDC timeout interrupt.

xtal16rdy_irq

XTAL16 oscillator ready interrupt. Clock is 16MHz (<50ppm) and 60/40 %

duty cycle

pll_lock_irq

Indicates that the PLL has locked at 96 MHz

Table 21: Interrupt list

IRQ

number

(inherent

priority)

IRQ name

Description

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