DA14683 datasheet(82/469 Pages) DIALOG

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Datasheet

Revision 3.4

24-Nov-2020

CFR0011-120-01

82 of 469

DA14683

Bluetooth Low Energy 5.0 SoC with Enhanced Security

FINAL

Note 3: Total Delay QSPI FLASH output + PCB delay + Tsux_qspi_dif < 1/Fqspi_sck.

E.g Winbond output + PCB delay = 6ns, -> Tsux_qspi_dif < 1/96MHz - 7 = 3.41 -> QSPI_PCLK_MD= 6, QSPI_RPIPE_EN=1 is recom-

mended value for all QSPI_SCK frequencies and shall be set before the maximum frequency is applied

Figure 48: QSPI Input Timing

Figure 49: QSPI output Timing

Table 29: QSPI bus timing (VDDIO = 1.8V, Cload=15 pF)

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNITS

Fqspi_sck

QSPI _SCK frequency

MHz

Td_qspi_do

Delay QSPI_SCK to QSPI_IOx

-1.4

Tdr_qspi_cs

Delay QSPI_SCK to QSPI_CS Tqspi_sck=1/Fqspi_sck

Tqspi_sck

- 2.5

Tqspi_sck

+2.0

Tdf_qspi_cs

Delay QSPI_CS to QSPI_SCK

Tqspi_sck=1/Fqspi_sck

Tqspi_sck

- 2.5

Tqspi_sck

+3.5

Tsu_qspi_dif

Setup time QSPI_IO to

QSPI_SCK falling edge with

variable readpipe sample clock

delay QSPI_RPIPE_EN=1

QSPIC_PCLK_MD=6

2.6

Thd_qspi_dif

Hold time QSPI_SCK falling

edge to QSPI_IO with variable

readpipe sample clock delay

QSPI_RPIPE_EN=1

QSPIC_PCLK_MD=6

-0.3

QSPI Output

Thd_qspi_dif

Tsu_qspi_dif

1/Fqspi_clk

QSPI_SCK

QSPI_IOx (input)

Td_qspi_do

Tdf_qspi_cs

Tdr_qspi_cs

MODE 3

MODE 0

MODE 3

MODE 0

QSPI_CS

QSPI_SCK

QSPI_IOx (output)

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