IMX53CEC datasheet(26/177 Pages) NXP

26 / 177 page

i.MX53xD Applications Processors for Consumer Products, Rev. 8

NXP Semiconductors

Electrical Characteristics

•

I/O Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede

NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is stabilized.

Within this group, the supplies can be powered-up in any order.

Alternatively, the on-chip regulator VDD_ANA_PLL can be used to power NVCC_CKIH and

NVCC_RESET. In this case, the sequence defined in the “Interfacing the i.MX53 Processor with

LTC3589-1” section of the i.MX53 System Development User's Guide (MX53UG) must be

followed.

•

I/O Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after

NVCC_CKIH is stable.

•

In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator

(default case for i.MX53xD), there are no related restrictions on VDD_REG, as it is used as their

internal regulators power source.

If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage

during the power-up, it is recommended to activate the VDD_REG before or at the same time with

VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that the 2.5 V

VDD_REG supply shut-off output impedance is higher than 1 k

Ω when it is inactive.

•

VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered on

after VCC and before NVCC_EMI_DRAM. The sequence should be:

VCC

→VDD_REG →NVCC_EMI_DRAM

•

If SRTC is not used, VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless

of any other power signal.

•

When SRTC is used, VDDA and VDDAL1 must be powered on before VDD_REG.

•

VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.

•

VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come

before POR.

•

TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This

is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is

powered ON before the other.

NOTE

The POR_B input must be immediately asserted at power-up and remain

asserted until after the last power rail reaches its working voltage.

NOTE

If NVCC_RESET power is removed or interrupted, a power-on reset is

generated.

IMX53CEC Datasheet(PDF) 26 Page - NXP Semiconductors

IMX53CEC Datasheet(HTML) 26 Page - NXP Semiconductors

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