IMX53CEC datasheet(56/177 Pages) NXP

56 / 177 page

i.MX53xD Applications Processors for Consumer Products, Rev. 8

NXP Semiconductors

Electrical Characteristics

4.6.6.4

Examples of EIM Synchronous Accesses

Figure 18 to Figure 21 provide few examples of basic EIM accesses to external memory devices with the

timing parameters mentioned previously for specific control parameters settings.

Figure 18. Synchronous Memory Read Access, WSC=1

1 t is the maximal EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum

allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be

≤ 104 MHz. If BCD = 1, then 133 MHz is allowed

for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 104 MHz, other busses are

impacted which are clocked from this source. See the CCM chapter of the i.MX53 Reference Manual for a detailed clock tree

description.

2 BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined

as 50% as signal value.

3 For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

Last Valid Address

Address v1

D(v1)

BCLK

ADDR

DATA

WE_B

ADV_B

OE_B

BEy_B

CSx_B

WE4

WE5

WE6

WE7

WE10

WE11

WE13

WE12

WE14

WE15

WE18

WE19

IMX53CEC Datasheet(PDF) 56 Page - NXP Semiconductors