IMX53CEC datasheet(13/177 Pages) NXP

13 / 177 page

Modules List

i.MX53xD Applications Processors for Consumer Products, Rev. 8

NXP Semiconductors

KPP

Keypad Port

Connectivity

Peripherals

The KPP supports an 8

× 8 external keypad matrix. The KPP features are

as follows:

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

LDB

LVDS Display

Bridge

Connectivity

Peripherals

LVDS display bridge is used to connect the IPU (image processing unit) to

external LVDS display interface. LDB supports two channels; each channel

has following signals:

• 1 clock pair

• 4 data pairs

On-chip differential drivers are provided for each pair.

OWIRE

One-Wire

Interface

Connectivity

Peripherals

One-wire support provided for interfacing with an on-board EEPROM, and

smart battery interfaces, for example, Dallas DS2502.

PATA

Parallel ATA

Connectivity

Peripherals

The PATA block is a AT attachment host interface. Its main use is to interface

with hard disk drives and optical disc drives. It interfaces with the ATA-6

compliant device over a number of ATA signals. It is possible to connect a

bus buffer between the host side and the device side.

PWM-1

PWM-2

Pulse Width

Modulation

Connectivity

Peripherals

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to

generate sound from stored sample audio images. It can also generate

tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate

sound.

INTRAM

Internal RAM

Internal

Memory

Internal RAM, shared with VPU.

The on-chip memory controller (OCRAM) module, is an interface between

the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is

used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus.

BOOTROM

Boot ROM

Internal

Memory

Supports secure and regular boot modes.

The ROM controller supports ROM patching.

RTIC

Run-Time

Integrity Checker

Security

Protecting read only data from modification is one of the basic elements in

trusted platforms. The run-time integrity checker, version 3 (RTIC) block is

a data-monitoring device responsible for ensuring that the memory content

is not corrupted during program execution. The RTIC mechanism

periodically checks the integrity of code or data sections during normal OS

run-time execution without interfering with normal operation. The purpose of

the RTIC is to ensure the integrity of the peripheral memory contents,

protect against unauthorized external memory elements replacement and

assist with boot authentication.

SAHARA

Security

Accelerator

Security

SAHARA (symmetric/asymmetric hashing and random accelerator),

version 4, is a security coprocessor. It implements symmetric encryption

algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA

and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and

a hardware true random number generator. It has a slave IP Bus interface

for the host to write configuration and command information, and to read

status information. It also has a DMA controller, with an AHB bus interface,

to reduce the burden on the host to move the required data to and from

memory.

Table 3. i.MX53xD Digital and Analog Blocks (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

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