SH7041A datasheet(157/923 Pages) RENESAS

Part #	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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157 / 923 page

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Section 7 User Break Controller (UBC)

7.1

Overview

The user break controller (UBC) provides functions that simplify program debugging. Break

conditions are set in the UBC and a user break interrupt is generated according to the conditions of

the bus cycle generated by the CPU, DMAC, or DTC. This function makes it easy to design an

effective self-monitoring debugger, enabling the chip to easily debug programs without using a

large in-circuit emulator.

7.1.1

Features

The features of the user break controller are:

• Break compare conditions can be set:

 Address

 CPU cycle or DMA/DTC cycle

 Instruction fetch or data access

 Read or write

 Operand size: byte/word/longword

• User break interrupt generated upon satisfying break conditions. A user-designed user break

interrupt exception processing routine can be run.

• Select either to break in the CPU instruction fetch cycle before the instruction is executed or

after.

7.1.2

Block Diagram

Figure 7.1 shows a block diagram of the UBC.

SH7041A Datasheet(PDF) 157 Page - Renesas Technology Corp