SH7041A datasheet(161/923 Pages) RENESAS

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UBAMRL:

Bit:

UBAMRL

UBM15

UBM14

UBM13

UBM12

UBM11

UBM10

UBM9

UBM8

Initial value:

R/W:

R/W

Bit:

UBAMRL

UBM7

UBM6

UBM5

UBM4

UBM3

UBM2

UBM1

UBM0

Initial value:

R/W:

R/W

• UBAMRH Bits 15–0—User Break Address Mask 31–16 (UBM31–UBM16): These bits

designate whether to mask any of the break address 31–16 bits (UBA31–UBA16) established

in the UBARH.

• UBAMRL Bits 15–0—User Break Address Mask 15–0 (UBM15–UBM0): These bits

designate whether to mask any of the break address 15–0 bits (UBA15–UBA0) established in

the UBARL.

Bits 15–0: UBMn

Description

Break address UBAn is included in the break conditions (initial value)

Break address UBAn is not included in the break conditions

Note:

n = 31–0

7.2.3

User Break Bus Cycle Register (UBBR)

User break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from

among the following four break conditions:

1. CPU cycle/ DMAC/DTC cycle

2. Instruction fetch/data access

3. Read/write

4. Operand size (byte, word, longword)

Resets and hardware standbys initialize the UBBR to H'0000. It is not initialized in software

standby mode.

SH7041A Datasheet(PDF) 161 Page - Renesas Technology Corp

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