BGU8821 datasheet(21/41 Pages) NXP

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NXP Semiconductors

BGU8821/A

Dual channel low-noise high linearity amplifier with DSA and SPDT

BGU8821/A

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Product data sheet

Rev. 6 — 15 April 2020

21 / 41

8.3 Device Functionality

The BGU8821/A supports both main and diversity receiver channels in both TDD and

FDD systems. It has a first stage LNA optimized for sensitivity followed by a digital step

attenuator and output stage amplifier. The first stage LNA output is routed outside the

device, so there is a possibility to use the device in different system configurations (e.g.

connect frequency selective filters in-between output of the first stage LNA and DSA

input, refer to Functional Diagram in Section 6).

Main and Diversity channels are controlled separately, via addressing different registers

in device’s memory. LNAs can be set in power-down mode to save current consumption

depending on system configuration (address 0x10h, refer to Table 18).

Attenuation levels of DSAs can be set with steps of 1 dB and total range of 31 dB.

Attenuation can be written to the address 0x11h for Main channel (Table 19) and the

address 0x12h for Diversity channel (Table 20).

To support highly integrated solutions and reduce platform costs a standalone SPDT

switch is included. Switch is controlled at address 0x13h (refer to Table 21).

All RF inputs and outputs are single-ended and matched to 50 Ω (external matching

components may be required, refer to Application information in Section 14). The

BGU8821/A is controlled via SPI bus, supporting both 3- and 4-wire configurations. Full

description of SPI interface is provided in Section 8.2. In TDD systems, the LNAs and

DSA can also be controlled via direct-access pins. The direct-access functionality is

described in Section 8.1.

BGU8821 Datasheet(PDF) 21 Page - NXP Semiconductors