BGU8821 datasheet(8/41 Pages) NXP

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NXP Semiconductors

BGU8821/A

Dual channel low-noise high linearity amplifier with DSA and SPDT

BGU8821/A

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Product data sheet

Rev. 6 — 15 April 2020

8 / 41

8.2.1 Hardware Interface description

The SPI functionality includes registers and an address decoder to support both read and

write operations. Register mapping is organized as a 15-bit address register and an 8-bit

data register. In order to avoid register coupling, data should always be sent as an 8-bit

sequence.

0x0Fh set the operation of the BGU8821/A. Any other address used does not affect the

behavior of the device (e.g. device does not stall).

The BGU8821/A supports a 3-wire or 4-wire SPI bus operation mode. <SDIO> is used

as a bidirectional pin in 3-wire mode. During the write cycle, it is used as an input pin and

during the read cycle as output pin. In 4-wire bus mode, <SDIO> and <SDO> are used

as unidirectional input and output pins correspondingly. <CLK> acts as the serial clock

input. The status of <CSB> defines whether the SPI interface of the device is enabled

(<CSB> is LOW) or disabled (<CSB> is HIGH). Programming clock edges (rising edges)

at <CLK> input and data at the <SDIO> input are ignored until LOW-level is applied to

the <CSB> input.

When the BGU8821/A is in power-down mode or there is no power supplied, the <SDIO>

and <CSB> pins become high-impedance and do not disturb the SPI bus.

8.2.2 Programming registers

The programming word is set through the input <SDIO> pin and a shift register, while

<CSB> level is LOW. To release the SPI bus, <CSB> is set HIGH again.

The rising edge of the clock pulse <CLK> shifts each data bit value into the shift register.

The BGU8821/A supports single-byte and multi-byte (streaming) read/write access

(register 0x01h bit [7]). In single-byte access, the new settings of the programmed

(streaming) access mode register address is auto-incremented or auto-decremented

(depends on register 0x00h bits [5] and [2]) for the next 8-bit programming word.

By default, the data is entered with the most significant bit (MSB) first and the least

significant bit (LSB) last. Register 0x00h bits [6] and [1] can be used to reverse the order

(LSB bit first).

Figure 3 and Figure 4 illustrate SPI read and write cycles for 3-wire and 4-wire modes.

aaa-020601

<SCLK>

<CSB>

<SDIO>

....

A09

A10

A11

A12

A13

A14

R/W

tCLK

tLo

tDH

tDS

tDV

tHi

Figure 3. SPI Single byte write 3-wire SPI bus

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