BGU8821 datasheet(13/41 Pages) NXP

13 / 41 page

NXP Semiconductors

BGU8821/A

Dual channel low-noise high linearity amplifier with DSA and SPDT

BGU8821/A

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Product data sheet

Rev. 6 — 15 April 2020

13 / 41

aaa-026526

Bit 7 6

NOT_USED

POWER_DOWN

Figure 7. Register address 0x02h

Table 10. Register address 0×02h

Legend: * reset value

Bits

Name

Access

Value

Description

7-2

NOT_USED

Not used

Sets power-down mode. In power-down mode all LNAs are disabled,

DSA's are in high attenuation mode. SPI bus is accessible and fully

functional. This register is double buffered. Active value is effective

after writing register 0x0Fh, bit [0]. Read value depends on setting of

00*

Normal operation

1-0

POWER_DOWN

R/W

Power-down mode

aaa-026533

Bit 7 6

NOT_USED

TRANSFER_BIT

Figure 8. Register address 0x0Fh

Table 11. Register address 0×0Fh

Legend: * reset value

Bits

Name

Access

Value

Description

7-1

NOT_USED

Not used

Transfer bit must be set HIGH to transfer the contents of the buffer

into the active register 0x02h

No transfer

TRANSFER_BIT

Transfer data into active registers. Bit value resets back to

LOW level after command is executed

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