NXP Semiconductors

BGU8821/A

Dual channel low-noise high linearity amplifier with DSA and SPDT

BGU8821/A

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2020. All rights reserved.

Product data sheet

Rev. 6 — 15 April 2020

4 / 41

7 Pinning information

7.1 Pinning

aaa-020600

exposed die pad

Transparent top view

terminal 1

index area

33

34

23

32

31

30

29

28

27

26

25

24

VDD_SPDT

VDD_SPI

GND/Disable Main channel

SW_RF2

GND

GND

SW_RFC

GND

GND

SW_RF1

GND/Disable Diversity channel

GPO/DSA_0_X dB Diversity

2

1

3

4

5

6

7

8

9

10

11

12

RFIN_M

GND

GND

GND

SCLK

CSB

SDIO

SDO

DSA_0_X dB Main

GND

RFIN_D

GND

Multiple power and ground pins allows for independent supply domains to improve cross channel isolation and between

blocks in one single channel. In, order to reduce series inductance at all RF ports and RF grounding a small package

footprint was chosen.

Figure 2. Pin configuration

7.2 Pin description

Table 5. Pin description

Symbol

Pin

Description

GND

1, 3, 4, 10, 12,

14,16, 17, 19, 20,

26, 27, 29, 30, 37,

38,40, 41,43

Ground

RFIN_M

2

RF Input to LNA1, main channel. An external DC block is required. External

SMD is required for matching.

SCLK

5

Clock input for SPI

CSB

6

Chip select active low

SDIO

7

Serial data in/out. Push-Pull pin

SDO

8

Serial data out. Push-Pull pin

DSA_0_X dB Main

9

Direct-access DSA setting between minimum attenuation and X dB

attenuation programmed prior to TDD mode, main channel