SY87700AL

DS20006628A-page 4



2021 Microchip Technology Inc. and its subsidiaries

2.0

PIN DESCRIPTIONS

Package Type

The descriptions of the pins are listed in Table 2-1.

SY87700AL

32-Lead TQFP (M)

(Top View)

TABLE 2-1:

PIN FUNCTION TABLE

Pin Number Pin Name

Description

Inputs

2

3

RDINP

RDINN

Serial Data Input. Differential PECL: These built-in line receiver inputs are connected to

the differential receive serial data stream. An internal receive PLL recovers the

embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be

within one of eight frequency ranges depending on the state of the FREQSEL pins. See

“Frequency Selection” Table.

5

REFCLK

Reference Clock. TTL Input: This input is used as the reference for the internal frequency

synthesizer and the “training” frequency for the receiver PLL to keep it centered in the

absence of data coming in on the RDIN inputs

26

CD

Carrier Detect. PECL Input: This input controls the recovery function of the Receive PLL

and can be driven by the carrier detect output of optical modules or from external

transition detection circuitry. When this input is HIGH the input data stream (RDIN) is

recovered normally by the Receive PLL. When this input is LOW the data on the inputs

RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain

LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced

to lock onto the clock frequency generated from REFCLK.

4

6

7

FREQSEL1

FREQSEL2

FREQSEL3

Frequency Select. TTL Inputs: These inputs select the output clock frequency range as

shown in the “Frequency Selection” Table.

32

25

DIVSEL1

DIVSEL2

Divider Select. TTL Inputs: These inputs select the ratio between the output clock

frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference

Frequency Selection” Table.

16

CLKSEL

Clock Select. TTL Input: This input is used to select either the recovered clock of the

receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL =

LOW) to the TCLK outputs.