SY87700AL datasheet(12/22 Pages) MICROCHIP

12 / 22 page

SY87700AL

DS20006628A-page 12

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2021 Microchip Technology Inc. and its subsidiaries

4.0

LAYOUT AND GENERAL SUGGESTIONS

• Establish controlled impedance stripline,

microstrip, or coplanar construction techniques.

• Signal paths should have approximately the same

width as the device pads.

• All differential paths are critical timing paths,

where skew should be matched to within ±10 ps.

• Signal trace impedance should not vary more

than ±5%. If in doubt, perform TDR analysis of all

high-speed signal traces.

• Maintain compact filter networks as close to filter

pins as possible. Provide ground plane relief

under filter path to reduce stray capacitance. Be

careful of crosstalk coupling into the filter network.

• Maintain low jitter on the REFCLK input. Isolate

the XTAL oscillator from power supply noise by

adequately decoupling. Keep XTAL oscillator

close to device, and minimize capacitive coupling

from adjacent signals.

• Higher speed operation may require use of

fundamental-tone (third-overtone typically has

more jitter) crystal-based oscillator for optimum

performance. Evaluate and compare candidates

by measuring TXCLK jitter.

• All unused outputs must be terminated. To

conserve power, unused PECL outputs can be

terminated with a 1 kΩ resistor to VEE.

SY87700AL Datasheet(PDF) 12 Page - Microchip Technology