SY87700AL datasheet(6/22 Pages) MICROCHIP

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SY87700AL

DS20006628A-page 6

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2021 Microchip Technology Inc. and its subsidiaries

3.0

FUNCTIONAL DESCRIPTION

Functional Block Diagram

3.1

Clock Recovery

Clock recovery, as shown in the block diagram,

generates a clock that is at the same frequency as the

incoming data bit rate at the serial data input. The clock

is phase aligned by a PLL so that it samples the data in

the center of the data eye pattern.

The phase relationship between the edge transitions of

the data and those of the generated clock are

compared by a phase/frequency detector. Output

pulses from the detector indicate the required direction

of phase correction. These pulses are smoothed by an

integral loop filter. The output of the loop filter controls

the frequency of the Voltage Controlled Oscillator

(VCO), which generates the recovered clock.

Frequency stability, without incoming data, is

guaranteed by an alternate reference input (REFCLK)

that the PLL locks onto when data is lost. If the

frequency of the incoming signal varies by greater than

approximately 1000 ppm with respect to the

synthesizer frequency, the PLL will be declared out of

lock, and the PLL will lock to the reference clock.

The loop filter transfer function is optimized to enable

the PLL to track the jitter, yet tolerate the minimum

transition density expected in a received SONET data

signal. This transfer function yields a 30 µs data stream

of continuous 1's or 0's for random incoming NRZ data.

3.2

Lock Detect

The SY87700AL contains a link fault indication circuit,

which monitors the integrity of the serial data inputs. If

the received serial data fails the frequency test, then

the PLL will be forced to lock to the local reference

clock. This will maintain the correct frequency of the

recovered clock output under loss of signal or loss of

lock conditions. If the recovered clock frequency

deviates from the local reference clock frequency by

more than approximately 1000 ppm, the PLL will be

declared out of lock. The lock detect circuit will poll the

input data stream in an attempt to reacquire lock to

data. If the recovered clock frequency is determined to

be within approximately 1000 ppm, the PLL will be

declared in lock and the lock detect output will go

active.

During the interval when the CDR is not locked onto the

RDIN input, the LFIN output will not be a static LOW,

but will be changing.

PHASE

DETECTOR

PHASE/

FREQUENCY

DETECTOR

CHARGE

PUMP

VCO

CHARGE

PUMP

VCO

LINK

FAULT

DETECTOR

DIVIDER

BY 8, 10, 16, 20

REFCLK

RDINN

RDINP

PLLR P/N

CLKSEL

RDOUTP

RCLKP

RCLKN

RDOUTN

LFIN

FREQSEL 1/2/3

PLLS P/N

DIVSEL 1/2

SY87700AL

TCLKP

TCLKN

VCC

VCCA

VCCO

GND

(PECL)

(TTL)

(PECL)

(TTL)

(PECL)

(TTL)

PHASE/

FREQUENCY

DETECTOR

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