AD8675 datasheet(30/60 Pages) AD

30 / 60 page

Data Sheet

AD3551R

THEORY OF OPERATION

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Rev. 0 | 30 of 60

SERIAL INTERFACE

The AD3551R implements a versatile serial interface that is com-

patible with several SPI modes. When the QSPI pin is tied low,

the interface is configured in single SPI (classic SPI) mode by

default and can be switched to dual SPI mode by acting on the

configuration registers. When the QSPI pin is pulled high, the

interface is configured in quad SPI mode. DDR can be enabled in

any of the modes to duplicate the transfer speed in the data phase.

Clock polarity (CPOL) can be 1 or 0, but clock phase (CPHA) must

be always 0. These combinations correspond to SPI Mode 0 and

Mode 3, which are applicable when the SPI interface is in single

data rate (SDR) mode.

Single SPI (Classic) Mode

In single SPI (classic) mode, the SDI/SDIO0 and SDO/SDIO1 data

lines are unidirectional. The SDI signal behaves as an input to

transfer data from master to slave and the SDO signal behaves as

an output to transfer data from slave to master, as shown in Figure

79. Single SPI (classic) mode is compatible with SPI Mode 0 and

Mode 3, as well as with completely synchronous interfaces, such

as synchronous serial port (SPORT™). See Figure 2 for a timing

diagram of a typical write sequence. See the AN-1248 Application

Note, SPI Interface, for more information about the classic SPI

mode.

Figure 79. Single SPI (Classic SPI) Connection

Dual SPI Mode

In dual SPI mode, the SDI/SDIO0 and SDO/SDIO1 data lines are

bidirectional, as shown in Figure 80. During the data phase, the

R/W bit of the instruction phase defines the direction of the data

lines. During the instruction phase, the data lines are always config-

ured as inputs. In dual SPI mode, consecutive bits are serialized in

groups of two, as shown in Figure 81.

Figure 80. Dual SPI Connection

Figure 81. Dual SPI Mode

AD8675 Datasheet(PDF) 30 Page - Analog Devices