AD9697 datasheet(40/130 Pages) AD

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AD9697

Data Sheet

Rev. 0 | Page 40 of 130

GPIO Level Control Mode

The GPIOx pins determine the exact NCO channel selected.

The following procedure must be followed to use GPIO level

control for NCO channel selection:

3. Configure one or more GPIOx pins as NCO channel

selection inputs. GPIOx pins not configured as NCO

channel selection are internally tied low.

a. To use GPIO1, write Bits[2:0] in Register 0x0040 to

0x6 and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO2, write Bits[5:3] in Register 0x0040 to

0x6 and Bits [7:4] in Register 0x0041 to 0x0.

4. Configure the NCO channel selector in GPIO level control

mode by setting Bits[7:4] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

desired GPIO pin ordering.

5. Select the desired NCO channel through the GPIOx pins.

GPIO Edge Control Mode

Low to high transition on the GPIOx pin determines the exact

NCO channel selected. The internal channel selection counter

is reset by either SYSREF± or the DDC soft reset.

The following procedure must be followed to use GPIO edge

control for NCO channel selection:

6. Configure one or more GPIOx pins as NCO channel

selection inputs.

a. To use GPIO1, write Bits[2:0] in Register 0x0040 to

0x6 and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO2, write Bits[5:3] in Register 0x0040 to

0x6 and Bits[7:4] in Register 0x0041 to 0x0.

7. Configure the NCO channel selector in GPIO edge control

mode by setting Bits[7:4] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

desired GPIOx pin.

8. Configure the wrap point for the NCO channel selection

by setting Bits[3:0] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

to wrap at Channel 4 (0, 1, 2, 3, 4, 0, 1, 2, 3, 4, and so on).

9. Transition the selected GPIOx pin from low to high to

increment the NCO channel selection.

NCO channel selection is controlled directly through the

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