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AD9697 Datasheet(PDF) 62 Page - Analog Devices

Part # AD9697
Description  14-Bit, 1300 MSPS, JESD204B, Analog-to-Digital Converter
PDF  130 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9697 Datasheet(HTML) 62 Page - Analog Devices

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AD9697
Data Sheet
Rev. 0 | Page 62 of 130
Register 0x056E must be programmed according to the lane
rate calculated. Refer to the Phase-Locked Loop (PLL) section
for more details.
Table 31 and Table 32 show the JESD204B output configurations
supported for both N΄ = 16, N’=12, and N΄ = 8 for a given
number of virtual converters. Take care to ensure that the serial
lane rate for a given configuration is within the supported range
of 1.6875 Gbps to 16 Gbps.
Table 31. JESD204B Output Configurations for N΄ = 161
Number
of Virtual
Converters
Supported
(Same as M)
JESD204B
Serial
Lane
Rate2
Supported Decimation Rates
JESD204B Transport Layer Settings3
Lane Rate =
1.6875 Gbps to
3.375 Gbps
Lane Rate =
3.375 Gbps to
6.75 Gbps
Lane Rate =
6.75 Gbps to
13.5 Gbps
Lane Rate =
13.5 Gbps to
16 Gbps
L
M
F
S
HD
N
N'
CS
K
1
20 × fOUT
2, 4, 5, 6
1, 2, 3
1
N/A
1
1
2
1
0
8 to 16
16
0 to 3
See
Note 4
20 × fOUT
2, 4, 5, 6
1, 2, 3
1
N/A
1
1
4
2
0
8 to 16
16
0 to 3
See
Note 4
10 × fOUT
1, 2, 3
1,
N/A
N/A
2
1
1
1
1
8 to 16
16
0 to 3
See
Note 4
10 × fOUT
1, 2, 3
1
N/A
N/A
2
1
2
2
0
8 to 16
16
0 to 3
See
Note 4
5 × fOUT
1
N/A
N/A
N/A
4
1
1
2
1
8 to 16
16
0 to 3
See
Note 4
5 × fOUT
1
N/A
N/A
N/A
4
1
2
4
0
8 to 16
16
0 to 3
See
Note 4
2
40 × fOUT
4, 8, 10, 12
2, 4, 5, 6
1, 2, 3
1
1
2
4
1
0
8 to 16
16
0 to 3
See
Note 4
40 × fOUT
4, 8, 10, 12
2, 4, 5, 6
1, 2, 3
1
1
2
8
2
0
8 to 16
16
0 to 3
See
Note 4
20 × fOUT
4, 5, 6
1, 2, 3
1
N/A
2
2
2
1
0
8 to 16
16
0 to 3
See
Note 4
20 × fOUT
2, 4, 5, 6
1, 2, 3
1
N/A
2
2
4
2
0
8 to 16
16
0 to 3
See
Note 4
10 × fOUT
1, 2, 3
1
N/A
N/A
4
2
1
1
1
8 to 16
16
0 to 3
See
Note 4
10 × fOUT
1, 2, 3
1
N/A
N/A
4
2
2
2
0
8 to 16
16
0 to 3
See
Note 4
4
80 × fOUT
8, 16, 20, 24
4, 8, 10, 12
2, 4, 6
2
1
4
8
1
0
8 to 16
16
0 to 3
See
Note 4
40 × fOUT
4, 8, 10, 12
2, 4, 5, 6
1, 2, 3
1
2
4
4
1
0
8 to 16
16
0 to 3
See
Note 4
40 × fOUT
4, 8, 10, 12
2, 4, 5, 6
1, 2, 3
1
2
4
8
2
0
8 to 16
16
0 to 3
See
Note 4
20 × fOUT
2, 4, 5, 6
1, 2, 3
1
N/A
4
4
2
1
0
8 to 16
16
0 to 3
See
Note 4
20 × fOUT
2, 4, 5, 6
1, 2, 3
1
N/A
4
4
4
2
0
8 to 16
16
0 to 3
See
Note 4
8
160 × fOUT
16, 40, 48
8, 16, 20, 24
4, 8, 12
4
1
8
16
1
0
8 to 16
16
0 to 3
See
Note 4
80 × fOUT
8, 16, 20, 24
4, 8, 10, 12
2, 4, 6
2
2
8
8
1
0
8 to 16
16
0 to 3
See
Note 4
40 × fOUT
4, 8, 10, 12
2, 4, 6
2
N/A
4
8
4
1
0
8 to 16
16
0 to 3
See
Note 4
40 × fOUT
4, 8, 10, 12
2, 4, 6
2
N/A
4
8
8
2
0
8 to 16
16
0 to 3
See
Note 4
1
Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
2
JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual
converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per
multiframe.
3
fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be
met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 16 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR
is ≤ 16,000 Mbps and > 13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13,500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR
is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50.
4
Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4,
8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.



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