AD9697 datasheet(21/130 Pages) AD

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Data Sheet

AD9697

Rev. 0 | Page 21 of 130

THEORY OF OPERATION

The AD9697 has a single analog input channel and up to four

JESD204B output lane pairs. The ADC samples wide bandwidth

analog signals of up to 2 GHz. The actual −3 dB roll-off of the

analog inputs is 2 GHz. The AD9697 is optimized for wide input

bandwidth, high sampling rate, excellent linearity, and low

power in a small package.

The ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. The

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations.

The AD9697 has several functions that simplify the AGC

function in a communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect output bits of the ADC. If the input

signal level exceeds the programmable threshold, the fast detect

indicator goes high. Because this threshold indicator has low

latency, the user can quickly turn down the system gain to avoid

an overrange condition at the ADC input.

The Subclass 1 JESD204B-based high speed, serialized output data

lanes can be configured in one-lane (L = 1), two-lane (L = 2),

and four-lane (L = 4) configurations, depending on the sample

rate and the decimation ratio. Multiple device synchronization

is supported through the SYSREF± and SYNCINB± input pins.

The SYSREF± pin in the AD9697 can also be used as a timestamp

of data as it passes through the ADC and out of the JESD204B

interface.

ADC ARCHITECTURE

The architecture of the AD9697 consists of an input buffered

pipelined ADC. The input buffer provides a termination

impedance to the analog input signal. This termination

impedance is set to 200 Ω. The equivalent circuit diagram of the

analog input termination is shown in Figure 33. The input

buffer is optimized for high linearity, low noise, and low power

across a wide bandwidth.

The input buffer provides a linear high input impedance (for

ease of drive) and reduces kickback from the ADC. The quantized

outputs from each stage are combined into a final 14-bit result

in the digital correction logic. The pipelined architecture permits

the first stage to operate with a new input sample; at the same

time, the remaining stages operate with the preceding samples.

Sampling occurs on the rising edge of the clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9697 is a differential buffer. The

internal common-mode voltage of the buffer is 1.41 V. The

clock signal alternately switches the input circuit between

sample mode and hold mode.

Either a differential capacitor or two single-ended capacitors (or

a combination of both) can be placed on the inputs to provide a

matching passive network. These capacitors ultimately create a

low-pass filter that limits unwanted broadband noise. For more

information, refer to the Analog Dialogue article “Transformer-

Coupled Front-End for Wideband A/D Converters”

(Volume 39, April 2005). In general, the precise front-end

network component values depend on the application.

Figure 44 shows the differential input return loss curve for the

analog inputs across a frequency range of 1 MHz to 10 GHz.

The reference impedance is 100 Ω.

1: 1.000MHz

170.59nF

2: 100.000 MHz

45.72pF

3: 200.000MHz

12.07pF

4: 300.000MHz

6.49pF

5: 400.000MHz

4.70pF

6: 500.000MHz

4.00pF

182.88Ω

–932.98mΩ

177.37Ω

–34.81Ω

157.29Ω

–65.95Ω

128.82Ω

–81.70Ω

102.55Ω

–84.58Ω

82.01Ω

–79.60Ω

CH1 AVG = 1

> CH1: START 1.0MHz

STOP 10.0000GHz

Figure 44. Different Input Return Loss

For best dynamic performance, the source impedances driving

VIN+ and VIN− must be matched such that any common-

mode settling errors are symmetrical. These errors are reduced

by the common-mode rejection of the ADC. An internal reference

buffer creates a differential reference that defines the span of the

ADC core.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. For the AD9697,

the available span is programmable through the SPI port from

1.36 V p-p to 2.04 V p-p differential, with 1.59 V p-p

differential being the default.

Differential Input Configurations

There are several ways to drive the AD9697, either actively or

passively. Optimum performance is achieved by driving the

analog input differentially.

For applications where SNR and SFDR are key parameters,

differential transformer coupling is the recommended input

configuration (see Figure 45 and Table 9) because the noise

performance of most amplifiers is not adequate to achieve the

true performance of the AD9697.

For low to midrange frequencies, a double balun or double

transformer network (see Figure 45 and Table 9) is recommended

for optimum performance of the AD9697. For higher frequencies

in the second or third Nyquist zones, it is recommended to

remove some of the front-end passive components to ensure

wideband operation (see Table 9).

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