AD9697 datasheet(29/130 Pages) AD

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Data Sheet

AD9697

Rev. 0 | Page 29 of 130

ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING

The AD9697 contains a configurable signal path that allows

different features to be enabled for different applications. These

features are controlled using the chip application mode register,

in this register, and the chip Q ignore is controlled by Bit 5.

The AD9697 contains the following modes:



Full bandwidth mode: 14-bit ADC core running at the full

sample rate.



DDC mode: up to four digital downconverter (DDC)

channels.

After the chip application mode is selected, the output

decimation ratio is set using the chip decimation ratio in

sample rate/the chip decimation ratio.

To support the different application layer modes, the AD9697

treats each sample stream (real, I, or Q) as originating from

separate virtual converters.

Table 11 shows the number of virtual converters required and

the transport layer mapping. Figure 65 shows the virtual

converters and their relationship to the DDC outputs when

complex outputs are used.

Each DDC channel outputs either two sample streams (I/Q) for

the complex data components (real + imaginary), or one sample

stream for real (I) data. The AD9697 can be configured to use up

to eight virtual converters, depending on the DDC configuration.

The I/Q samples are always mapped in pairs with the I samples

mapped to the first virtual converter and the Q samples mapped

to the second virtual converter. With this transport layer mapping,

the number of virtual converters are the same whether a single

real converter is used along with a digital downconverter block

producing I/Q outputs, or whether an analog downconversion

is used with two real converters producing I/Q outputs.

Figure 66 shows a block diagram of the two scenarios described

for I/Q transport layer mapping.

Table 11. Virtual Converter Mapping

No. of Virtual

Converters

Supported

Chip Operating

Mode

(Reg. 0x0200,

Bits[3:0])

Chip Q Ignore

(0x0200, Bit 5)

Virtual Converter Mapping

Full bandwidth

mode (0x0)

Real or complex

(0x0)

ADC

samples

Unused

One DDC mode

(0x1)

Real (I only)

(0x1)

DDC 0 I

samples

Unused

One DDC mode

(0x1)

Complex (I/Q)

(0x0)

DDC 0 I

samples

DDC 0 Q

samples

Unused

Two DDC mode

(0x2)

Real (I only)

(0x1)

DDC 0 I

samples

DDC 1 I

samples

Unused

Two DDC mode

(0x2)

Complex (I/Q)

(0x0)

DDC 0 I

samples

DDC 0 Q

samples

DDC 1 I

samples

DDC 1 Q

samples

Unused

Four DDC mode

(0x3)

Real (I only)

(0x1)

DDC 0 I

samples

DDC 1 I

samples

DDC 2 I

samples

DDC 3 I

samples

Unused

Four DDC mode

(0x3)

Complex (I/Q)

(0x0)

DDC 0 I

samples

DDC 0 Q

samples

DDC 1 I

samples

DDC 1 Q

samples

DDC 2 I

samples

DDC 2 Q

samples

DDC 3 I

samples

DDC 3 Q

samples

DDC 3

OUTPUT

INTERFACE

CONVERTER 7

REAL/I

CONVERTER 6

DDC 2

CONVERTER 5

REAL/I

CONVERTER 4

DDC 1

CONVERTER 3

REAL/I

CONVERTER 2

REAL

DDC 0

CONVERTER 1

REAL/I

CONVERTER 0

REAL

REAL/I

ADC

SAMPLING

Figure 65. DDCs and Virtual Converter Mapping

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