AD9697 datasheet(23/130 Pages) AD

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Data Sheet

AD9697

Rev. 0 | Page 23 of 130

Using Register 0x1A4C and Register 0x1A4D, the buffer behavior

can be adjusted to optimize the SFDR over various input

frequencies and bandwidths of interest. Use Register 0x1910 to

change the internal reference voltage. Changing the internal

reference voltage results in a change in the input full-scale voltage.

When the input buffer current in Register 0x1A4C and

AVDD3 supply changes. This relationship is shown in Figure 48.

For a complete list of buffer current settings, see Table 10.

0.050

0.020

400

350

450

500

BUFFER CURRENT (µA)

300

0.025

0.030

0.035

0.040

0.045

Figure 48. AVDD3 Current (IAVDD3) vs. Buffer Current (Buffer Control 1 Setting in

Table 10 shows the recommended values for the buffer current

for various Nyquist zones.

Absolute Maximum Input Swing

The absolute maximum input swing allowed at the inputs of the

AD9697 is 5.6 V p-p differential. Signals operating near or at

this level can cause permanent damage to the ADC.

Dither

The AD9697 has internal on-chip dither circuitry that improves

the ADC linearity and SFDR, particularly at smaller signal

levels. A known but random amount of white noise is injected into

the input of theAD9697. This dither improves the small signal

linearity within the ADC transfer function and is precisely

subtracted out digitally. The dither is turned on by default and

does not reduce the ADC input dynamic range. The data sheet

specifications and limits are obtained with the dither turned on.

The dither is on by default. It is not recommended to turn it off.

Table 10. SFDR Optimization for Input Frequencies

Speed Grade

Frequency

AD9697-1300

All AIN frequencies

300 µA

0x02

0xC1

0x00

ADC

CORE

INPUT FULL-SCALE

RANGE ADJUST

SPI REGISTER

(0x1910)

VREF PIN

CONTROL SPI

(0x18A6)

VFS

ADJUST

VIN+

VIN–

VREF

INTERNAL

0.5V

REFERENCE

GENERATOR

Figure 49. Internal Reference Configuration and Controls

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