AD9772A-EB datasheet(7/40 Pages) AD

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AD9772A

Rev. C | Page 7 of 40

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

DIGITAL INPUTS

Logic 1 Voltage

2.1

Logic 0 Voltage

0.9

Logic 1 Current1

−10

+10

μA

Logic 0 Current

−10

+10

μA

Input Capacitance

CLOCK INPUTS

Input Voltage Range

Common-Mode Voltage

0.75

1.5

2.25

Differential Voltage

0.5

1.5

PLL CLOCK ENABLED (SEE Figure 2)

Input Setup Time (tS)

TA = 25°C

1.5

TA = −40 to +85°C

2.1

Input Hold Time (tH)

TA = 25°C

1.3

TA = −40 to +85°C

1.6

Latch Pulse Width (tLPW), TA = 25°C

1.5

PLL CLOCK DISABLED (SEE Figure 3)

Input Setup Time (tS)

TA = 25°C

−0.7

TA = −40 to +85°C

−0.4

Input Hold Time (tH)

TA = 25°C

3.3

TA = −40 to +85°C

3.7

Latch Pulse Width (tLPW), TA = 25°C

1.5

CLK+/CLK− to PLLLOCK Delay (tOD)

TA = 25°C

1.9

2.8

TA = −40 to +85°C

1.8

3.3

PLLLOCK (VOH), TA = 25°C

3.0

PLLLOCK (VOL), TA = 25°C

0.3

1 MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 μA.

0.025%

DB0 TO DB13

CLK+ – CLK–

IOUTA

IOUTB

tLPW

tPD

tST

Figure 2. Timing Diagram—PLL Clock Multiplier Enabled

DB0 TO DB13

0.025%

IOUTA

IOUTB

tOD

PLLLOCK

CLK+ – CLK–

tLPW

tPD

tST

Figure 3. Timing Diagram—PLL Clock Multiplier Disabled

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