RT600 datasheet(85/167 Pages) NXP

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RT600

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Product data sheet

Rev. 2.0 — 1 April 2022

85 of 165

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

• Data can be transferred using DMA from deep-sleep mode without waking up the

CPU, then automatically returning to deep-sleep mode.

• Data can be streamed directly to I2S on Flexcomm Interface 7.

10.19.3 CRC engine

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings

supports several CRC standards commonly used. To save system power and bus

bandwidth, the CRC engine supports DMA transfers.

10.19.3.1 Features

• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

– CRC-CCITT: x16 + x12 + x5 + 1

– CRC-16: x16 + x15 + x2 + 1

– CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

• Bit order reverse and 1’s complement programmable setting for input data and CRC

sum.

• Programmable seed number setting.

• Supports CPU PIO or DMA back-to-back transfer.

• Accept any size of data width per write: 8, 16 or 32-bit.

– 8-bit write: 1-cycle operation.

– 16-bit write: 2-cycle operation (8-bit x 2-cycle).

– 32-bit write: 4-cycle operation (8-bit x 4-cycle).

10.20 Analog peripherals

10.20.1 12-bit Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12-bit and fast conversion rates of up to 1Msamples/s.

Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible

trigger sources are the SCTimer/PWM, external pins, and the Arm TXEV interrupt.

The ADC supports a variable clocking scheme with clocking synchronous to the system

clock or independent, asynchronous clocking for high-speed conversions

The ADC includes a hardware threshold compare function with zero-crossing detection.

The threshold crossing interrupt is connected internally to the SCTimer/PWM inputs for

tight timing control between the ADC and the SCTimer/PWM.

10.20.1.1 Features

• 12-bit successive approximation analog to digital converter.

• Input multiplexing among up to 12 pins.

• Two configurable conversion sequences with independent triggers.

• Optional automatic high/low threshold comparison and “zero crossing” detection.

• Measurement range VREFN to VREFP (typically 1.8 V; not to exceed

VDDA_ADC1V8 voltage level).

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