RT600 datasheet(88/167 Pages) NXP

88 / 167 page

RT600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.0 — 1 April 2022

88 of 165

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

10.21.8 Universally Unique Identifier (UUID)

The RT600 stores a 128-bit IETF RFC4122 compliant non-sequential Universally Unique

Identifier (UUID). It can be read from registers SYSCTL0_UUID0 through

SYSCTL0_UUID3

10.21.9 Device Identifier Composition Engine (DICE)

The RT600 supports Device Identifier Composition Engine (DICE) to provide Composite

Device Identifier (CDI). CDI value would be available in registers

SYSCTL0DICEHWREG0 through SYSCTL0DICEHWREG7 for consumption after boot

completion. It is recommended to overwrite these registers once ephemeral key-pairs are

generated using this value.

10.22 Emulation and debugging

Debug and trace functions are integrated into the Arm Cortex-M33. Serial wire debug and

trace functions are supported. The Arm Cortex-M33 is configured to support up to eight

breakpoints and four watch points.

The Arm SYSREQ reset is supported and causes the processor to reset the peripherals,

execute the boot code, restart from address 0x0000 0000, and break at the user entry

point.

The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the

SWD functions by default.

RT600 Datasheet(PDF) 88 Page - NXP Semiconductors