AD2428W datasheet(6/38 Pages) AD

6 / 38 page

Rev. C

Page 6 of 38

July 2021

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)

I2S Reduced Rate

Slave transceivers can run the I2S/TDM/PDM interface at a

reduced rate frequency, with respect to the superframe rate. The

reduced rate frequency is derived by dividing the superframe

rate from a programmable set of values. Different slave nodes

can be configured to run at different reduced I2S/TDM rates.

The transceiver provides an option for a processor to track the

full rate audio frame, which contains new reduced rate samples.

The IO7 pin can be used as a strobe, and the direction can be

configured as an input or output.

PULSE DENSITY MODULATION (PDM) INTERFACE

The PDM block on the transceiver converts a PDM input

stream into pulse code modulated (PCM) data to be sent over

the A2B bus and/or out to the local node through the I2S/TDM

port. It supports high dynamic range microphones with high

signal-to-noise ratio (SNR) and extended maximum sound

pressure level. The PDM interface supports 12 kHz and 24 kHz

frame rates in addition to a 48 kHz frame rate and can be used

on both master and slave transceivers.

Even lower PDM sampling rates (for example, down to 375 Hz)

are possible in combination with the reduced rate feature of the

transceiver. The cutoff frequency of the high-pass filter in the

transceiver PDM block is fixed to 1 Hz.

BCLK can be used to clock PDM microphones on a slave, but if

PDMCLK/IO7 is used instead, the BCLK frequency can be set to

a different frequency using the I2S/TDM registers. In this case,

PDMCLK/IO7 is used as the PDM clock (PDMCLK) to capture

PDM input on DRX0/DRX1. The clock rate from PDMCLK is

64× the SYNC frequency.

On a master node, BCLK is always an input, so the clock to

PDM microphones that are attached to a master typically comes

from PDMCLK/IO7. It is possible to use BCLK to drive the

PDM clock inputs on a master node, but this restricts the possi-

ble TDM settings because BCLK is required to fall within the

fBCLK specification in Table 4.

BCLK and PDMCLK/IO7 can also be used concurrently to

clock PDM microphones at the same frequency and phase

alignment, but with opposite polarity. Additionally, a register

setting selects whether rising edge data or falling edge data is

sampled first.

GPIO OVER DISTANCE

The transceiver supports general-purpose input/output (GPIO)

between multiple nodes without host intervention after initial

programming. The host is required only for initial setup of the

GPIO bus ports. I/O pins of different nodes can be logically OR

or AND gate combined.

MAILBOXES

The transceiver supports interrupt driven, bidirectional mes-

sage exchange between I2C master devices (microcontrollers) at

different slave nodes and the host connected to the master node

transceiver in two dedicated mailboxes. The mailboxes can be

used to customize handshaking among numerous nodes in a

system to coordinate system events, such as synchronizing

audio.

DATA SLOT EXCHANGE BETWEEN SLAVES

Using the DTX0 and DTX1 pins, slave transceivers can selec-

tively output upstream or downstream data that originates from

other nodes without the need for data slots to be routed through

the master node. Receive data channels can be skipped based on

a programmable offset, when the data is presented as upstream

or downstream slots to the A2B bus.

CLOCK SUSTAIN STATE

In the clock sustain state, audio signals of locally powered slave

nodes are attenuated in the event of lost bus communication.

When the bus loses communication and a reliable clock cannot

be recovered by the slave node, the slave node transceiver enters

the sustain state and, if enabled, signals this event to a GPIO pin.

In the clock sustain state, the phase-locked loop (PLL) of the

slave node transceiver continues to run for 1024 SYNC periods,

while attenuating the I2S DTX0 to DTX1 data from the current

value to 0. After the 1024 SYNC periods, the slave node trans-

ceiver resets and reenters the power-up state.

PROGRAMMABLE SETTINGS TO OPTIMIZE EMC

PERFORMANCE

The following programmable features can be used to improve

electromagnetic compatibility (EMC) performance.

Programmable LVDS Transmit Levels

The low voltage differential signal (LVDS) transmitter can be set

to transmit the signal at high, medium, or low levels. Higher

transmit levels yield greater immunity to EMI, whereas lower

transmit levels can reduce emissions from the twisted-pair

cables that link A2B bus nodes together. The improved LVDS

receiver (compared to other members of the AD242xW family)

maintains robust operation when transmit levels are lowered.

Spread-Spectrum Clocking

Spread-spectrum clocking can be used to reduce narrow-band

emissions on a printed circuit board (PCB). Spread-spectrum

clocking is disabled on the transceiver by default, but spread-

spectrum clocking for all internal clocks can be enabled during

discovery by a register write.

If spread-spectrum clocking support is enabled for the internal

clocks, spread-spectrum clocking can also be enabled for both

the I2S interface and the programmed CLKOUTs. Enabling

spread-spectrum clocking for internal clocks, CLKOUTs, and

the I2S interface may reduce narrow-band emissions by several

dB on a particular node. When spread-spectrum clocking is

enabled on a clock output, the time interval error (TIE) jitter on

that clock increases.

Unique ID

Each transceiver contains a unique ID, which can be read from

registers using software. If a read of the unique ID fails, an inter-

rupt can be generated.

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