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PCA2117DUGS/DA Datasheet(PDF) 44 Page - NXP Semiconductors

Part # PCA2117DUGS/DA
Description  Automotive LCD driver for character displays
PDF  107 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA2117DUGS/DA Datasheet(HTML) 44 Page - NXP Semiconductors

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PCA2117
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2015
44 of 107
NXP Semiconductors
PCA2117
Automotive LCD driver for character displays
[1]
No temperature compensation is possible above 105
C. Above this value, the system maintains the
compensation value from 105
C.
8.4.5.3
Example calculation of Voffset(LCD)
Assumed that Tamb = 8 C
1. Choose a temperature factor from Table 35, for example TSB[2:0] = 001, which gives
a slope factor of
0.125.
2. Calculate the decimal value of TD[7:0] with Equation 4:
.
3. Calculate the temperature compensating factor VT with the appropriate equation from
Table 36:
.
4. Calculate Voffset(LCD) with Equation 2:
.
8.4.6 LCD bias voltage generator
The intermediate bias voltages for the LCD are generated on-chip. It removes the need for
an external resistive bias chain and significantly reduces the system current consumption.
The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth)
and the number of bias levels.
The intermediate bias levels for the different multiplex rates are shown in Table 37. These
bias levels are automatically set to the given values when switching to the corresponding
multiplex rate.
Table 36.
Calculation of the temperature compensating factor VT
Temperature range (
C) Decimal value of TD[7:0] Equations of factor VT
0
0 to 48
49 to 96
97 to 143
144 to 230
[1]
231
T40
C
–
VT
48
–
TSB
48
TSA
–
=
40
C
–
T
10
C
–
VT
48
–
TSB
48
TD[7:0]
–
 TSA
–
=
10
C
–
T
20
C
VT
96
TD[7:0]
–
 TSB
–
=
20
CT50 C
VT
TD[7:0]
96
–
 TSC
=
50
CT 105 C

VT
47
TSC
TD[7:0]
143
–
 TSD
+
=
105
CT
VT
47
TSC
88
TSD
+
=
TD
8
–
40
+
0.6275
-------------------
51
=
VT
96
51
–

–
0.125
–
5.625
==
V
offset LCD

5.625
0.03 V
0.169 V
==
Table 37.
Bias levels as a function of multiplex rate
Multiplex
rate
LCD bias
configuration
Bias voltages
V1
V2
V3
V4
V5
V6
1:18
1⁄4
VLCD
VSS
1:9
1⁄4
VLCD
VSS
1:2
1⁄3
VLCD
VSS
3
4
---V
LCD
1
2
---V
LCD
1
2
---V
LCD
1
4
---V
LCD
3
4
---V
LCD
1
2
---V
LCD
1
2
---V
LCD
1
4
---V
LCD
2
3
---V
LCD
2
3
---V
LCD
1
3
---V
LCD
1
3
---V
LCD



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