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PCA2117DUGS/DA Datasheet(PDF) 10 Page - NXP Semiconductors |
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PCA2117DUGS/DA Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 107 page ![]() PCA2117 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 8 April 2015 10 of 107 NXP Semiconductors PCA2117 Automotive LCD driver for character displays 8.1.1.3 Command: Clear_reset_flag The Clear_reset_flag command clears the reset flag CRF, see Table 12 on page 11. 8.1.1.4 Command: OTP_refresh In order to achieve the specified accuracy of the VLCD, the frame frequency, and the temperature measurement, each IC is calibrated during production. These calibration values are stored in One Time Programmable (OTP) cells. Their content is loaded into the associated registers every time when the Initialize command or the OTP_refresh command is sent. This command takes approximately 10 ms to finish. 8.1.1.5 Command: Clock_out_ctrl When pin CLK is configured as an output pin, the Clock_out_ctrl command enables or disables the clock output on pin CLK. [1] Default value. For lower power consumption, the clock is only active when display (see Table 25), charge pump (see Table 30), or temperature measurement (see Table 32) is enabled. Table 7. Initialize - Initialize command bit description Bit Symbol Value Description -R/W 0 fixed value - RS[1:0] 00 fixed value 7 to 0 - 00000001 initialize Table 8. Clear_reset_flag - Clear_reset_flag command bit description Bit Symbol Value Description -R/W 0 fixed value - RS[1:0] 00 fixed value 7 to 0 - 00011111 clear reset status flag Table 9. OTP_refresh - OTP_refresh command bit description Bit Symbol Value Description -R/W 0 fixed value - RS[1:0] 00 fixed value 7 to 0 - 00000010 refresh register settings from OTP Table 10. Clock_out_ctrl - CLK pin input/output switch command bit description Bit Symbol Value Description -R/W 0 fixed value - RS[1:0] 00 fixed value 7 to 1 - 0010000 fixed value 0COE CLK pin setting 0[1] clock signal not available on pin CLK; pin CLK is in 3-state 1 clock signal available on pin CLK |
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