PCA2117DUGSSLASHDA datasheet(85/107 Pages) NXP

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PCA2117

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Product data sheet

Rev. 4 — 8 April 2015

85 of 107

NXP Semiconductors

PCA2117

Automotive LCD driver for character displays

14. Dynamic characteristics

14.1 General timing characteristics

14.2 I2C-bus timing characteristics

[1]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS1 to VDD1.

[2]

tVD;DAT = minimum time for valid SDA output following SCL LOW.

[3]

tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.

Table 51.

General dynamic characteristics

VDD1, VDD2 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 16.0 V; Tamb = 40 C to +105 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fclk(int)

internal clock

frequency

on pin CLK; Tamb =25 C;

FF[4:0] = 00111

61600

64000

66400

fclk(ext)

external clock

frequency

on pin CLK

36000

288000

tclk(H)

HIGH-level clock time

external clock source used

s

tclk(L)

LOW-level clock time

s

Table 52.

I2C-bus timing characteristics

VDD1, VDD2 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 16.0 V; Tamb = 40 C to +105 C; unless otherwise specified.[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCL

SCL frequency

400

kHz

tBUF

bus free time between

a STOP and START

condition

1.3

s

tHD;STA

hold time (repeated)

START condition

0.6

s

tSU;STA

set-up time for a

repeated START

condition

0.6

s

tVD;DAT

data valid time

[2] --

0.9

s

tVD;ACK

data valid

acknowledge time

[3] --

0.9

s

tLOW

LOW period of the

SCL clock

1.3

s

tHIGH

HIGH period of the

SCL clock

0.6

s

fall time

of both SDA and SCL signals

0.3

s

rise time

of both SDA and SCL signals

0.3

s

capacitive load for

each bus line

400

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

tSU;STO

set-up time for STOP

condition

0.6

s

tw(spike)

spike pulse width

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