PCA2117DUGSSLASHDA datasheet(65/107 Pages) NXP

65 / 107 page

PCA2117

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Product data sheet

Rev. 4 — 8 April 2015

65 of 107

NXP Semiconductors

PCA2117

Automotive LCD driver for character displays

consequence it may be possible that the acknowledge cycle, generated by the LCD driver,

cannot be interpreted as logic 0 by the master. Therefore it is an advantage for COG

applications to have the acknowledge output separated from the data line. For that

reason, the SDA line of the PCA2117 is split into SDAIN and SDAOUT.

In COG applications where the acknowledge cycle is required, it is necessary to minimize

the track resistance from the SDAOUT pin to the system SDAIN line to guarantee a valid

LOW level.

By splitting the SDA line into SDAIN and SDAOUT (having the SDAOUT open circuit), the

device could be used in a mode that ignores the acknowledge cycle. Separating the

acknowledge output from the serial data line can avoid design efforts to generate a valid

acknowledge level. However, in that case the I2C-bus master has to be set up in such a

way that it ignores the acknowledge cycle.2

By connecting pin SDAOUT to pin SDAIN the SDAIN line becomes fully I2C-bus

compatible (see Figure 45). The following definition assumes that SDAIN and SDAOUT

are connected and refers to the pair as SDA.

9.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

are interpreted as a control signal (see Figure 46).

9.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START

condition (S).

For further information, consider the NXP application note: Ref. 1 “AN10170”.

Fig 45. SDAOUT and SDAIN configuration

Fig 46. Bit transfer

PCA2117DUGS/DA Datasheet(PDF) 65 Page - NXP Semiconductors