PCA2117DUGSSLASHDA datasheet(105/107 Pages) NXP

105 / 107 page

PCA2117

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Product data sheet

Rev. 4 — 8 April 2015

105 of 107

NXP Semiconductors

PCA2117

Automotive LCD driver for character displays

26. Figures

Fig 1.

Block diagram of PCA2117 . . . . . . . . . . . . . . . . . .4

Fig 2.

Pinning diagram of PCA2117DUGx . . . . . . . . . . . .5

Fig 3.

Example of the display shift . . . . . . . . . . . . . . . . .17

Fig 4.

Example of a linefeed . . . . . . . . . . . . . . . . . . . . .21

Fig 5.

Illustration of the display configuration bits . . . . .23

Fig 6.

Recommended start-up sequence when using

the internal charge pump and the internal clock

signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Fig 7.

Recommended start-up sequence when using an

externally supplied VLCD and the internal clock

signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Fig 8.

Recommended start-up sequence when using

the internal charge pump and an external clock

signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Fig 9.

Recommended start-up sequence when using an

externally supplied VLCD and an external clock

signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 10. Recommended power-down sequence for

minimum power-down current when using the

internal charge pump and the internal clock

signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Fig 11. Recommended power-down sequence when

using an externally supplied VLCD and the

internal clock signal . . . . . . . . . . . . . . . . . . . . . . .33

Fig 12. Recommended power-down sequence when

using the internal charge pump and an external

clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Fig 13. Recommended power-down sequence when

using an externally supplied VLCD and an

external clock signal . . . . . . . . . . . . . . . . . . . . . .34

Fig 14. Connecting PCA2117 with a 2 ´ 20 character

LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Fig 15. Connecting PCA2117 with a 1 ´ 40 character

LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Fig 16. Typical system configuration if using the

internal VLCD generation and I2C-bus . . . . . . . . .36

Fig 17. Typical system configuration if using the

external VLCD and SPI-bus . . . . . . . . . . . . . . . . .36

Fig 18. VLCD generation including temperature

compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Fig 19. VLCD programming of PCA2117 (assuming

VT[8:0] = 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Fig 20. VLCD with respect to Iload at VDD2 = 2.5 V . . . . . .40

Fig 21. VLCD with respect to Iload at VDD2 = 5 V . . . . . . . .40

Fig 22. VLCD with respect to Iload at VDD2 = 5 V . . . . . . . .41

Fig 23. Temperature measurement block with digital

temperature filter . . . . . . . . . . . . . . . . . . . . . . . . .42

Fig 24. Temperature measurement delay . . . . . . . . . . . .42

Fig 25. Example of segmented temperature

coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 26. Electro-optical characteristic: relative

transmission curve of the liquid . . . . . . . . . . . . . .46

Fig 27. Waveforms for the 1:18 multiplex drive mode.

5 bias levels, character mode, frame inversion

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fig 28. Waveforms for the 1:9 multiplex drive mode,

5 bias levels, character mode, R8 to R15

and R17 open, frame inversion mode . . . . . . . . . 48

Fig 29. Waveforms for the 1:2 multiplex drive mode,

4 bias levels, icon mode, frame inversion mode . 49

Fig 30. Dataflow from CGROM, CGRAM and ICON-RAM

to the display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Fig 31. RAM/ROM access flowchart . . . . . . . . . . . . . . . . 51

Fig 32. Logic diagram of the CRC8 generator . . . . . . . . 52

Fig 33. Checksum generation . . . . . . . . . . . . . . . . . . . . . 52

Fig 34. Character set ‘R’ in CGROM . . . . . . . . . . . . . . . . 53

Fig 35. Character set ‘S’ in CGROM . . . . . . . . . . . . . . . . 54

Fig 36. Configuration of CGROM and CGRAM with

RR[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Fig 37. User-defined euro currency sign . . . . . . . . . . . . . 57

Fig 38. Icon to row/column mapping . . . . . . . . . . . . . . . . 60

Fig 39. DDRAM to display mapping: no shift . . . . . . . . . 61

Fig 40. DDRAM to display mapping: right shift . . . . . . . . 61

Fig 41. DDRAM to display mapping: left shift . . . . . . . . . 61

Fig 42. Cursor and blink display examples . . . . . . . . . . . 63

Fig 43. Display example with icons . . . . . . . . . . . . . . . . . 63

Fig 44. Control byte format . . . . . . . . . . . . . . . . . . . . . . . 64

Fig 45. SDAOUT and SDAIN configuration. . . . . . . . . . . 65

Fig 46. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Fig 47. Definition of START and STOP conditions . . . . . 66

Fig 48. System configuration. . . . . . . . . . . . . . . . . . . . . . 66

Fig 49. Acknowledgement on the I2C-bus. . . . . . . . . . . . 67

Fig 50. SPI data transfer overview . . . . . . . . . . . . . . . . . 72

Fig 51. Device protection diagram . . . . . . . . . . . . . . . . . 76

Fig 52. Typical IDD1 with respect to temperature . . . . . . . 82

Fig 53. Typical IDD2 with respect to temperature . . . . . . . 82

Fig 54. Typical IDD(LCD) with respect to temperature . . . . 83

Fig 55. Typical VLCD variation with respect to

temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Fig 56. Typical frame frequency variation with respect

to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Fig 57. Measurement temperature variation with respect

to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Fig 58. Driver timing waveforms . . . . . . . . . . . . . . . . . . . 86

Fig 59. I2C-bus timing diagram . . . . . . . . . . . . . . . . . . . . 86

Fig 60. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Fig 61. Bare die outline of PCA2117DUGx . . . . . . . . . . . 89

Fig 62. Alignment marks . . . . . . . . . . . . . . . . . . . . . . . . . 93

Fig 63. Tray details of PCA2117DUGx . . . . . . . . . . . . . . 95

Fig 64. Die alignment in the tray . . . . . . . . . . . . . . . . . . . 96

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