AD4685 datasheet(18/32 Pages) AD

18 / 32 page

Data Sheet

AD4684/AD4685

MODES OF OPERATION

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Rev. 0 | 18 of 32

The AD4684/AD4685 have several on-chip configuration registers

for controlling the operational mode of the device.

CHANNEL SELECTION

The ADC channel pairs for conversion (AINA0 and AINB0, AINA1

and AINB1) are selected by setting the CH bit in the CONFIGURA-

TION1 register. If the CH bit is set to 0, the AINA0 and AINB0

channels simultaneously convert. Alternatively, if the CH bit is set

to 1, the AINA1 and AINB1 channels are selected for simultaneous

conversion.

If the channel to convert is changing, the ADC requires addition-

al settling time. The maximum throughput rate when changing

between the AINx0 and AINx1 channels is 500 kSPS for the AD4684

and 250 kSPS for the AD4685.

SEQUENCER

The AD4684/AD4685 can be configured to automatically cycle

through the AINx0 and AINx1 channels using the on-chip sequencer.

The sequencer is controlled via the SEQ bit in the CONFIGURA-

TION1 register. If the SEQ bit is set to 0, the sequencer is disabled.

If SEQ is set to 1, the sequencer is enabled. The CH bit is not

queried for the sequencer mode. The sequencer always starts at

the AINx0 channels and then moves to the AINx1 channels. After

converting the AINx1 channel, the sequencer loops back to the

AINx0 channels and the sequence restarts.

If the channel to convert is changing, the ADC requires addition-

al settling time. The maximum throughput rate when changing

between AINx0 and AINx1 channels is 500 kSPS for the AD4684

and 250 kSPS for the AD4685.

Figure 34 shows the manual channel selection setup, and Figure 35

shows the channel sequencer setup.

Figure 34. Manual Channel Selection Setup

Figure 35. Channel Sequencer Setup

AD4685 Datasheet(PDF) 18 Page - Analog Devices